The present invention relates to a semiconductor device and a manufacturing method therefor, and, more particularly, to an effective technique applicable to a semiconductor device including a fin transistor.
The fin transistor is known as a field effect transistor, which has a high operation speed, and can reduce the leakage current and power consumption and can be miniaturized. The fin transistor (FINFET: FIN Field Effect Transistor) is a semiconductor element, having, for example, a semiconductor layer which projects over the semiconductor substrate as a channel region and having a gate electrode which is formed across and over the projecting semiconductor layer.
As an electrically writable and erasable non-volatile memory, a flash memory and an EEPROM (Electrically Erasable and Programmable Read Only Memory) are widely used. These memory units have, below the gate electrode of MISFET (Metal Insulator Semiconductor Field Effect Transistor), a conductive floating gate electrode surrounded by an oxide film or a trap insulating film, assume a charge storage state in the floating gate electrode or the trap insulating film as storage information, and read it as a threshold voltage of the transistor. This trap insulating film represents a charge storage insulating film, and is, for example, a silicon nitride film. Injection and discharge of charges to and from this charge storage layer cause the threshold voltage of the MISFET to shift, and cause it to operate as a storage element. An example of this flash memory, a split gate-type cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure.
International Publication 2010/082389 discloses a technique for preventing a short circuit between a control gate electrode and a contact plug, by providing an insulating film on the upper part of the control gate electrode of a non-volatile memory.
Specification of U.S. Unexamined Patent Application Publication No. 2013/0256767 discloses a technique for preventing a short circuit between the contact plug for a drain region and a gate electrode, by applying the gate electrode having a gate last structure in the FINFET and providing an insulating film on the upper part of the gate electrode.
Japanese Unexamined Patent Application Publication No. 2017-045860 discloses a technique for forming a non-volatile memory with the FINFET structure.